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Word Aligner
SV52002
2014.01.07
Serial protocols such as PCIe specify a standard word alignment pattern. For proprietary protocols, the
transceiver architecture allows you to select a custom word alignment pattern specific to your implementation.
In addition to restoring the word boundary, the word aligner also implements the following features:
?
?
?
?
?
Synchronization state machine in configurations such as PCIe
Programmable run length violation detection in all configurations
Receiver polarity inversion in all configurations except PCIe
Receiver bit reversal in custom configurations
Receiver byte reversal in custom 16- and 20-bit width configurations
Depending on the configuration, the word aligner operates in one of the following modes:
? Manual alignment
? Automatic synchronization state machine
? Bit-slip
Table 1-6: Word Aligner Options
Configuration
PMA-PCS
Interface Width
Word Alignment Word Alignment
Mode
Pattern Length
Word Alignment Behavior
(Bits)
8
Manual
Alignment
Bit-Slip
16 bits
16 bits
User-controlled signal starts
the alignment process.
Alignment happens once unless
the signal is reasserted.
User-controlled signal shifts
data one bit at a time.
Custom 8- and 10-Bit
Width
Manual
Alignment
7 and 10 bits
User-controlled signal starts
the alignment process.
Alignment happens once unless
the signal is reasserted.
10
Bit-Slip
7 and 10 bits
User-controlled signal shifts
data one bit at a time.
Automatic
7 and 10 bits
Data is required to be 8B/10B
Altera Corporation
Synchronized
State Machine
encoded. Aligns to the selected
word aligner pattern.
Transceiver Architecture in Stratix V Devices
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